Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
EDN

Designers debate ‘VHDL is dead’ assertion

SANTA CRUZ, Calif. — Recent reports of remarks by Aart de Geus, Synopsys CEO, stating that SystemVerilog will replace VHDL caused a torrent of commentary in Thursday's (April 24) E-Mail Synopsys Users ...
Design-Reuse

Aldec(R) Releases RTL Simulator with Enhanced Assertions and Xilinx(R) SecureIP Support

HENDERSON, Nev.-- December 21, 2009--Aldec Corporation, a leader in RTL Simulation and Electronic Design Automation (EDA), releases its latest RTL and gate-level simulator, Active-HDLâ„¢ 8.2 sp1, for ...
EDN

VHDL-200x improves design and verification productivity

VHDL is a critical language for RTL design and is a major component of the $200+ million RTL simulation market 1. Many users prefer VHDL for RTL design because the language continues to provide ...