TechRepublic

32 Bit Parallel Multiplier Using VHDL

In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High ...
EDN

16-bit pipelined serial/parallel multiplier using Mentor Graphics Tools

Designed the 16-bit pipelined serial/parallel multiplier by utilizing the MOSIS (TSMC) 0.35 μm CMOS process. The 16-bit Pipelined Serial/Parallel Multiplier is capable of multiplying two 16-bit ...
EDN

Architecture-oriented C optimization, part 1: DSP features

Part 2 looks at memory-related optimizations. It will be published September 3. Know your hardware! That's what it's all about. Using programming guidelines derived from the processor's architecture ...
Design-Reuse

Design and implementation of Parallel and Pipelinined Distributive Arithmetic based Discrete Wavelet Transform IP core

The Discrete Wavelet Transform (DWT) has gained the reputation of being a very effective signal analysis tool for many practical applications. This paper presents an approach towards VLSI ...
Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
manilatimes

MicroCloud Hologram Inc. Develops Serial-Parallel Architecture-Based FPGA Quantum Computing Simulation Framework

SHENZHEN, China, Dec. 22, 2025 (GLOBE NEWSWIRE) -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO” or the "Company"), a technology service provider, launched a brand-new FPGA-based quantum computing ...