The PCIe specification has given a specific Link Training and Status State Machine (LTSSM) state named Loopback, which is intended for test and fault isolation use. Basically, it gives a mechanism ...
Today's methods for BER (bit-error-rate) testing of high-speed serial links such as PCIe and SATA rely on predetermined patterns that don't represent real-world situations. These patterns use a ...
Read more from the April issue. Sunnyvale, CA —High-speed serial buses such as PCIe (PCIExpress) and 10-Gbps Ethernet present significant challenges to designers ofcomputers and communications systems ...
IRVINE, Calif.--(BUSINESS WIRE)--DesignCon - Menlo Microsystems, Inc. (Menlo Micro), the company responsible for bringing to market the greatest electronic component innovation since the transistor ...
January 29, 2013. Agilent Technologies Inc. at DesignCon announced an enhanced solution for PCI Express 3.0 receiver characterization. The Agilent PCIe 3.0 receiver characterization solution provides ...
Tektronix Inc. has released a draft method of implementation (MOI) for PCI Express 3.0 receiver testing using the BERTScope BSA85C. This complements previously introduced solutions for verifying ...
Cadence stole the show recently at the PCI-SIG DevCon 2024 event, and in honor of the 32nd anniversary of the PCI-SIG Developer's Conference, Cadence announced a complete PCIe 7.0 IP solution for HPC ...
A promising solution for economical precision test can take your jitters out of jitter testing. Multigigabit high-speed serial (HSS) interfaces like PCI Express, Fibre Chan-nel, XAUI, and Serial ATA ...
IRVINE, Calif.--(BUSINESS WIRE)--Menlo Microsystems, Inc. (Menlo Micro), the company responsible for bringing to market the greatest electronic component innovation since the transistor with its Ideal ...
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