Design-Reuse

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process ...
EDN

Memory fault models and testing

A different set of fault models and testing techniques is required for memory blocks vs. logic. MBIST algorithms that are used to detect faults inside memory are based upon these fault models. This ...
Electronic Design

Logical block addressing comes to NAND Flash

Logical block addressing (LBA) for NAND Flash memory—that's what Toshiba says its done with the LBA-NAND, a new range of high-capacity devices integrating the new addressing method. NAND Flash memory ...
Electronic Design

Structured ASICs

So what’s a STRUCTURED ASIC? A Structured ASIC is a type of integrated circuit that contains blocks of logic, called "tiles." These tiles reside in the die ready to be connected in a customizable ...