EDN

Synopsys’ New DesignWare DDR Explorer Tool Delivers Up to 20 Percent Improvement in DDR Memory Subsystem Efficiency

DesignWare DDR Explorer enables designers to optimize memory subsystems for power, performance and cost through a graphical simulation and analysis environment Explore and adjust Synopsys' DesignWare ...
Design-Reuse

AccelChip DSP Synthesis with IP-Explorer Technology to be demonstrated at SDR Forum

Paper to be presented on finite-precision effects of the matrix inversion techniques when used in a Generalized Sidelobe Canceling (GSC) beamformer MILPITAS, CA – November 8, 2005 – AccelChip Inc.
Electronic Design

Synthesis Tool Suite Speeds DSP Design

With multiple tools being brought to bear on the process of DSP design and synthesis, the AccelDSP Synthesis 8.1 tool and AccelWare DSP libraries of algorithmic IP make short work of FPGA-based DSP ...
Business Wire

Cadence Extends Digital Design Leadership with Revolutionary ML-based Cerebrus, Delivering Best-in-class Productivity and Quality of Results

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence ® Cerebrus™ Intelligent Chip Explorer, a new machine learning (ML)-based tool ...